BAe, Movellus team for clock IP in space

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The FAST labs of BAE Systems has signed a deal with Movellus in the US to use its Intelligent Clock Network IP for space designs. The design and implementation of rad-hard electronics platforms for space systems can be very time consuming and prohibitively expensive. Movellus’ Radiation Hardened by Design (RHBD),…
By Nick Flaherty

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The FAST labs of BAE Systems has signed a deal with Movellus in the US to use its Intelligent Clock Network IP for space designs.

The design and implementation of rad-hard electronics platforms for space systems can be very time consuming and prohibitively expensive. Movellus’ Radiation Hardened by Design (RHBD), process portable, all-digital Intelligent Clock Network IP simplifies the design process and enables greater performance.

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BAE Systems will include the Movellus TrueDigital IP with its rad-hard ASIC technologies and libraries to deliver a complete, advanced development solution for creating system-on-chip designs for its portfolio of rad-hard electronics for civil, commercial, and national security missions.

The Movellus Maestro platform combines a clock architecture, software automation, and application-optimized IP to solve common clocking challenges. It addresses problems such as on-chip variation, jitter, clock skews, peak current, and switching noise, all of which are increasing with advanced process scaling using the TrueDigital all-digital PLLs and DLLs reduce power consumption and better operating characteristics compared to traditional analog and partial-digital solutions. These can operate at ultra-low nanowatt voltages and high performance multi-Ghz frequencies while occupying only a small footprint.

The IP includes a master RTL codebase that can be configured to generate code that precisely meets application specifications. Its fully synthesizable architectures enable rapid RTL-to-GDS implementation and optimization and the Maestro Phases tool is designed to work seamlessly with existing digital tools and methodologies to reduce design complexity in SOC designs such as video signal processing, frequency synthesis, clock synchronization, demodulation, precision timing, and improved clock signal quality. The IP is silicon-proven across foundries including TSMC, GF, UMC, and Fujitsu and also supports implementations for non-standard process nodes.

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