imec charts path beyond 1nm
比利时研究实验室IMEC已将半导体工艺技术和芯片设计的途径绘制在1NM以下到A2 Two Angstrom生成。
“We are convinced that Moore’s Law will not stop, but there will be many approaches that will all contribute,” said Luc van den Hove, CEO of imec at the Futures conference.
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He points to several generations of device architecture, evolving from FinFET devices to forksheet and atomic channel devices, as well as new materials and the introduction of high NA lithography systems by ASML which takes many years. The prototype NA systems being installed now will see commercial roll out in 2024.
“We are confident that the lithography tools will be there to extend Moore’s Law well beyond the equivalent 1nm generation. But we will need to develop new device architectures. This will allow the shrinking of a standard cell,” he said.
Finfet一直是10nm降至3nm的主力。“从2NM大门围绕着建筑，由一堆纳米片建造，将是最有可能的概念。”
He points to the forksheet architecture developed at imec. This allows us to put the n and p channel closer together with a barrier material. This will be an option to extend gate all around beyond 1nm. Then you can put the n and p channel on top of each other for further scaling and we believe we have developed the first versions of these.”
然后是使用钨或钼的新材料，可以为2028年及以下A10（1nm）过程提供几个原子的栅极长度，以在2034年在2034年的四个Angstrom（A4）和2036年在2036年具有四个Angstrom（A4）的结构。
“We recently demonstrated first versions of these atomic channel devices. These will bring us to the sub 1nm generations,” he said.
- Applied upgrade supports backside power and GAA transistors
- Delivering power from the back of a chip
“But we also need to improve the performance of the interconnect. One interesting option is to move the power delivery to the back of the wafer. This leaves more design flexibility for the interconnect on the front side.
“All of this results in scaling for the next fifteen to twenty years,” he said.
To realise the benefits of all these we need a paradigm shift to more domain specific architectures, he says. Future system on chip devices will be integrated as a 3D stack of chips using through silicon via (TSV) and microbump technologies, for example stacking an SRAM memory for the L1 cache right on top of the core logic and using chiplets with different process technologies for different tasks. This leads to multiple 3D chips can be connected on a silicon interposer.
“We have been developing all these enabling technologies that are gradually being picked up by industry as we speak,” he said.
“我们需要考虑这些设备制造的可持续性，用电，水，化学品。在优化这些过程时，不足以查看性能，力量和领域，但我们必须考虑到这些技术的环境方面，”
