新解决方案基于ALDEC的HES-MPF500-M2S150原型板。
“Aldec has a long history of developing hardware assisted verification solutions, with our first HES board and simulation acceleration platform released 20 years ago,” said Zibi Zalewski, General Manager of Aldec’s Hardware Division. “We also have a proven track record of developing Microsemi/Microchip FPGA prototyping boards, and it is great that we can combine these areas of expertise to meet today’s verification challenges.”
Mostsimulation acceleration techniques are based on FPGAs from one or two FPGA vendors.Normally which FPGA family is used on the simulation acceleration boarddoesn’t really matter too much asthe designwill becoded using synthesizable RTL.
However, a growing number of designs are increasing in complexity,which is compounded by the pressing need for shorter设计周期和a desire to get to market quicker.This has led toan increasing amount of engineersmaking use of可重复使用的IP块from the FPGA vendor, instead of developingtheRTL codethemselves。Th这意味着开发人员是locked into thegiven FPGA technology.These可重复使用的IP块normally needmuchmore computational power to simulate than pure RTL code.
Aldec’s HES-DVM was developed to overcomethesechallenges and remove a key verification bottleneck.The新的release of theEDA tool允许users of PolarFire, RTAX/RTSX and SmartFusion2 devices to take advantage of Microchip IPstoaccelerate RTL simulationswithAldec’s HES-MPF500-M2S150.The board is based around thelargest devices available in both families.
Zalewski concludes: “During the 20 years since we introduced HES, the world of digital designs has changed significantly and the need for simulation speeds to increase has grown along with not only design complexity but also the size and features of FPGAs. Our latest release of HES-DVM will be of great benefit to designers using Microchip IPs.”
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