The recent Design and Verification Conference & Exhibition Europe (DVCon Europe) saw registrations reach a record high of 465, covering 149 organisations and 24 countries.
The show, organised with the Accellera standards group for system-level design, modeling, and verification standards, featured a full Virtual Reality (VR) 3D world, modelled on a conference centre in Munich, with 24 papers, 13 tutorials and two panels.
"This year we really changed the way in which people could talk to each other at the ‘virtual conference’ and it was very gratifying to hear from fellow participants that they had never experienced such a rich virtual environment,” said Mark Burton, Virtual Platform Chair and founder and CEO of French SystemC and virtual platform expert GreenSoC.
Burton joined with vice chair Joachim Geishauser from NXP Semiconductors, and technical programme chair Alexander Rath from Infineon to assess the trends in the verification industry foreeNews Europe. This follows announcements from ARM ahead of the conference on new ways to access virtual prototype for software development and continuous integration and continuous development (CI/CD) methodologies.
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“We had a lot of papers about verification of bigger SoCs where the scalability of the test bench and the configurability was an issue so its about how to architect a verification,” said Rath. “That’s something perhaps even the UVM standardisation committee perhaps needs to look at.”
“We are pretty good at verifying blocks and midsized chips but Europe does big mixed signal chips for automotive where you have many challenges apart from the SOCs just being big, with analog, digital and software, it’s an enormous systemic complexity that is hard to quantify,“ he said. “Then on top of that there are the challenges of functional safety, how to make the verification systemically consistent so that a car will not do any harm
“In automotive world especially there are rising security standards with new standards. That’s kind of funny as security and safety have an overlap but in other cases they are entirely separate – you can’t just shut everything off if you get a security alert when you are running 150km/h on the highway. One way is to have a very rigid thorough engineering approach. Another approach is virtual prototyping,” he said.
“I was particularly struck by the focus on virtual prototypes that up until now have been seen as getting software engineers up and running quicker for continuous integration (CI) and test which is booming right now but also being used to address safety and security issues,” said Mark Burton at GreenSoC.
“I feel like it’s taken the next step and we are seeing a lot in automotive. There’s a lot of silos in the industry. Aerospace and defence have been doing safety and security for donkeys years and they have their own methodologies and languages and their own virtual platforms and their own standards. Airbus for example would love to use commercial off the shelf (COTS) devices and are asking for models to particular standards and this is a live action for Accellera to address.”
“Integrating security depends on the virtual prototype,” he says. “There are hybrid models with FPGAs and SystemC models and there’s a lot of flexibility in the software virtual prototype to blow up a design it up in any way. But the way it responds is not necessarily the way the real hardware will respond. Companies like Airbus have been doing this for decades and there is a lot of knowledge there and there is a lot of communication with automotive designers.”
He sees the role of virtual prototyping changing. “In the past it’s been an additional check rather than replacing a check,” he said. “It means I can develop the verification quicker on the virtual prototype for a minimum set of tests to prove the original functional definition.”
“If there is a safety or security alert, virtual prototypes are good to make sure the system as a whole still runs correctly,” said Rath. “What you can’t really do on a virtual prototype is intrusion testing, detecting hacks or safety problems, this needs to be verified on a level closer to the implementation
“The virtual platforms can help you get to the right set of tests, and as an additional test in the virtual environment,” said Burton.
“There are two issues,” says Geishauser. “Security built into software that can be verified with virtual prototype but there is also security built into the hardware and this needs assessment with formal methods.”
“The other factor that is also driving the designs is the increasing size of devices,” he said. “The tools are not able to handle the size and you need to partition the complete SoC and that forces the verification to align with the partitions and then use a modular hierarchical verification.”
