SiPearl backs Ansys for power sign-off of Rhea and Cronos chips
European supercomputer chip designer SiPearl is adopting Ansys Redhawk-SC for power sign-off in its high performance computing projects.
The Rhea chip is being developed by Sipearl as part of the European Processor Initiative (EPI) consortium for exascale supercomputing. SiPearl will use the Ansys RedHawk-SC multiphysics simulation platform to validate semiconductor power integrity, minimize power consumption, and accelerate development of the family of chips.
Ansys’ high predictive accuracy multiphysics simulation platform is used to minimize chip power and ensure operational reliability.
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“Ansys’ industry-leading simulation platform will enable us to ensure the low-power performance and reliability of our microprocessor,” said Philippe Notton, CEO and founder of SiPearl. “With Ansys’ world-class RedHawk-SC signoff solution, we can achieve industry-leading performance and deliver our prototype in a timely manner to power Europe’s supercomputer of the future.”
The first-generation family of microprocessors, known as Rhea, is planned for next year, with a second-generation family of microprocessors, known as Cronos, planned for launch in 2023-2024.
“Power management has become an essential primary concern for chip designers at advanced silicon processes,” said John Lee, vice president and general manager of the electronics, semiconductor, and optics business unit at Ansys. “We are collaborating with the silicon foundries and major semiconductor customers to develop our high-capacity simulation platforms that integrate multiple physical effects to ensure high-fidelity results and the fastest time-to-results.”
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