TSMC certifies Synopsys and Cadence tools for 3nm process
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The certification, based on the latest TSMC N3 3nm design-rule manual (DRM) and process design kits, results from extensive, multi-year collaboration to deliver co-optimized tools, flows and methodologies.
The process is aimed at large chips for high-performance computing (HPC), mobile, 5G and AI chip designs. These chip designers are already using Synopsys tools for ARM’s latest processor cores on 3nm processes:
“TSMC’s leading-edge technology required new levels of EDA collaboration and innovation to deliver on the high performance and low-power goals of the 3nm process technology,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Our long-term collaboration with Synopsys has helped accelerate access to, and the maximization of the benefits from, TSMC’s latest process offering. We will continue to work closely together to enable next-generation designs for HPC, Mobile, 5G, and AI applications.”
“By broadening our collaboration with Cadence, we’re providing our customers with certified flows and PDKs they need to quickly adopt the advanced TSMC N3 and N4 process technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “We’ve seen our customers successfully complete test chip designs and tapeouts on our latest advanced processes and are looking forward to our continued partnership with Cadence to enable next-generation designs for mobile, automotive, AI, and hyperscale applications.”
Synopsys对此的高度集成融合设计平台is a critical part of this successful advanced-node collaboration, delivering comprehensive, full-flow design convergence and tight signoff correlation for TSMC’s 3nm technology. Synopsys’ Fusion Compiler and the IC Compiler ll place-and-route product, achieve optimized timing quality-of-results (QoR) through new global and detail-route technology innovations. Full-flow, total-power optimization advancements and concurrent-legalization-and-optimization technology enable the achievement of the required total-power profiles and the overall optimized PPA design metrics.
Other implementation technologies deployed as part of the 3nm collaboration include support for advanced routing with colouring and via-pillar consideration and innovative flip-flop optimization that aids both performance-focused and low-power designs. The Design Compiler NXT synthesis product, a key component of the Fusion Design Platform, has also been enhanced to provide a more convergent design flow through tighter timing correlation to IC Compiler II, benefiting all designs targeting the N3 process.
The Synopsys 3nm collaboration with TSMC also includes PrimeTime support for low-voltage variation and supports TSMC’s placement rules to enable convergent ECO closure during both implementation and signoff. Synopsys’ PrimePower supports 3nm physical rules for power signoff, including leakage and dynamic power along with StarRC extraction-modeling enhancements to deliver the needed accuracy.
Additional signoff solutions certified for TSMC 3nm technology include NanoTime custom timing signoff, ESP custom equivalence verification and QuickCap NX parasitic field solver solution. The IC Validator physical signoff has been enhanced to support all advanced-process requirements, including new dummy-fill features for improved density, layout-dependent effects for layout-versus-schematic checking, and enhanced delta-voltage rule-debug efficiency for DRC.
众多增强自定义编译器、验证d by early 3nm users including the Synopsys DesignWare IP team, reduce the effort to meet 3nm technology requirements. Designers are also using the PrimeSim Continuum SPICE simulators to improve turnaround time for TSMC 3nm designs and provide signoff coverage for circuit simulation and reliability requirements.
“Both the ecosystem and our customers benefit from TSMC’s and Synopsys’ close collaborations to push the achievable limits and accelerate access to each new technology process,” said Shankar Krishnamoorthy, general manager and corporate staff for the Digital Design Group at Synopsys. “Our latest digital and custom R&D collaborations for the 3nm technology have delivered new levels of technology innovation to overcome the challenges of the process and thus open up a new chapter of opportunities for our mutual customers to deliver on their advanced-product roadmaps in a timely manner.”
The Cadence digital flow has also been tuned and certified for use on TSMC’s N3 and N4 process technologies. The complete RTL-to-GDS flow includes the Innovus Implementation System, Liberate Characterization Solution, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option and Voltus IC Power Integrity Solution for electromigration and IR drop analysis. In addition, the Genus Synthesis Solution and its predictive iSpatial technology is enabled for these process technologies.
Advanced rule support from synthesis to signoff engineering change orders (ECOs); large libraries containing many multi-height, voltage threshold (VT) and drive strength cells; and low-voltage call characterization and timing analysis accuracy. Custom design flow enhancements for TSMC’s N3 and N4 process technologies include an enhanced N3 schematic design migration flow and advanced coloring feature support for both N3 and N4 processes.
“Our latest collaboration with TSMC has enabled mutual customers to leverage the combined benefits of TSMC’s N3 and N4 process technologies using our digital flow and custom flow,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Our customers have achieved positive results already, and we’re looking forward to enabling more incredible innovations, which stem from our dedication to SoC design excellence.”
www.synopsys.com/tsmc;www.cadence.com
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