3D die-on-die IP for TSMC 5nm process
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Taiwanese chip designer Global Unichip Corp (GUC) has launched 3D die-to-die interconnect for TSMC’s 5nm N5 and N6 process technology for AI, HPC, and networking chips.
AI，HPC和网络芯片中对内存的需求正在迅速增长，SRAM与逻辑比率也在增加。当缩放到N5/N3过程节点时，逻辑会获得更高的密度和性能，但是SRAM从7nm N7过程缩放到N5和N3是中等的。
GUC’s GLink-3D achieved six times higher bandwidth/area density, six times lower latency and twice lower power consumption than its previous 2.5D interface (GLink-2.0) that taped out in Dec 2020.
Separating out the SRAM and logic allows the most efficient process nodes, but requires new assembly techniques in the packaging. Layers of CPU and SRAM die for cache and packet buffers dies can be assembled over and under interconnect/IO dies using TSMC’s 3DFabric packaging technology.
Such expandable SRAM and modular computing applications are enabled by GUC GLink-3D high bandwidth, low latency, low power, and point-to-multipoint interface between 3D stacked dies. This allows the CPUs, SRAMs, interconnects and I/Os such as SerDes, HBM, DDR to all be implemented in different process nodes, with different die combinations assembled to address different market segments. At boot time, assembled SRAM and CPU dies are identified, unique die IDs are distributed, available memory space and computing resources are defined and a point-to-multipoint GLink-3D interface to the stacked dies is enabled.
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TSMC’s 3DFabric SoIC platform technology allows more efficient connectivity as several 3D die stacks can be assembled using CoWoS and InFO_oS, interconnected using GLink-2.5D links and combined with HBM memories.
“ Glink-3D是一流和硅经验丰富的HBM2E/3 PHY/Controller和Glink-2.5D IP的丰富投资组合的新成员。Cowos，Info_os，3DIC专业知识，包装设计，电气和热模拟，DFT和生产测试在一个GUC屋顶下为我们的ASIC客户提供快速的设计周期，快速提高和生产坡道。”。
“ 3D模具堆叠技术将以我们设计HPC，AI和网络处理器的方式开始革命。Die-die接口不再限于Die Boundare，它可以确切地找到处理器需要连接到SRAM和其他CPU的位置。3DFABRIC和GLINK-3D铺平了未来处理器的方式，将巨大，可扩展的处理能力与庞大，高带宽和低潜伏期内存相结合，使用最有效的过程节点实现每个组件。”GUC首席技术官Igor Elkanovich说。
GLink-3D supports TSMC-SoIC stacking of combination of N5 and N6 process nodes with point-to-multipoint interface allows the main die to interface with several stacked dies simultaneously and full duplex 9Tbps traffic per mm2 at 5.0 Gbps per lane. The end-to-end latency is under 2ns with low power design of less than 0.2pJ/bit from a single supply voltage of 0.75V±10％。
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