TSMC shows 2nm nanosheet transistor plans for 2025 production
Foundry TSMC has detailed a new 3nm process technology and its plans for 2nm using nanosheet transistors.
The 3nm Finflex process is set to enter production later this year and has transistor with different number of fins for different applications. There are cells with a 3-2 fin configuration for high performance, a 2-1 fin configuration for best power efficiency and transistor density, and a 2-2 fin configuration providing a balance between the two.
2NM N2工艺从FinFets转移到纳米片晶体管。这将在相同的功率上提供10％至15％的速度提高，或以相同速度的降低25％至30％。除了移动计算基线版本以及Chiplet Integration技术，还将有一个高性能的变体。N2计划于2024年在2025年开始采样。
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TSMC is also developing N6e, an ultra low power process for the next evolution in process technology tuned to provide the computing power and energy efficiency required by edge AI and IoT devices. N6e will be based on TSMC’s 7nm process and is expected to have three times greater logic density than the current low power process, N12e.
TSMC has also been showcasing two customer applications of its TSMC-SoIC chip stacking technology. The world’s first SoIC-based CPU uses Chip-on-Wafer (CoW) technology to stack SRAM as a Level 3 cache, while GraphCore’s Bow intelligence processing unit AI chip is stacked on top of a deep trench capacitor die using Wafer-on-Wafer (WoW) technology.
- Apple goes to 2.5D for 114bn transistor M1 Ultra
- Graphcore boosts AI performance with wafer-on-wafer tech
TSMC说，N7 7NM工艺中建造的芯片已经在牛和哇，并且计划在2023年对N5技术的支持。对这种堆叠技术的需求正在增长，TSMC计划在2022年下半年开放世界上第一个完全自动化的3Dfabric工厂。
“We are living in a rapidly changing, supercharged, digital world where demand for computational power and energy efficiency is growing faster than ever before, creating unprecedented opportunities and challenges for the semiconductor industry,” said Dr. C.C. Wei, CEO of TSMC. “The innovations we will showcase at our Technology Symposiums demonstrate TSMC’s technology leadership and our commitment to support our customers through this exciting period of transformation and growth.”
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